1. Field of the Invention
The present invention relates to a dynamic random access memory (DRAM) cell, as well as methods for operating and fabricating a DRAM cell. More specifically, the present invention relates to a vertical one-transistor floating-body DRAM cell formed using a process compatible with a bulk CMOS process, wherein charge is stored inside an electrically isolated body region adjacent to the transistor channel region.
2. Related Art
Conventional one-transistor, one-capacitor (1T/1C) DRAM cells require a complex process for fabrication. Moreover, significant area is required to form the capacitor needed for storage of signal charge. Recently, one-transistor, floating-body (1T/FB) DRAM cells using partially-depleted silicon-on-insulator (PD-SOI) processes have been proposed, in which a signal charge is stored inside a floating body region, which modulates the threshold voltage (VT) of the transistor. As a result, the separate capacitor of a 1T/FB DRAM cell can be eliminated, thereby resulting in reduced cell area and higher density. Periodic refresh operations are still required for these 1T/FB DRAM cells to counteract the loss of stored charge through junction leakage, gate tunneling leakage and access-induced hot-carrier injections (HCI).
FIG. 1 is a cross-sectional view of a conventional 1T/FB DRAM cell 100 fabricated using a PD-SOI process. DRAM cell 100 includes silicon substrate 101, buried oxide layer 102, oxide regions 103–104, N++ type source and drain regions 105–106, N+ type source and drain regions 107–108, P type floating body region 109, gate oxide 110, gate electrode 111 and sidewall spacers 112–113. Floating body 109 is isolated by gate oxide 110, buried oxide layer 102 and the source and drain depletion regions 107′ and 108′. The partially-depleted floating body 109 is used for storing signal charges that modulate the threshold voltage (VT) of DRAM transistor 100 differently when storing different amount of charge. The source node 105 is typically grounded.
A logic “1” data bit is written into DRAM cell 100 by biasing drain node 106 at a high voltage and gate node 111 at a mid-level voltage to induce hot-carrier injection (HCI), whereby hot-holes are injected into floating body node 109, thereby raising the voltage level of floating body node 109, and lowering the threshold voltage (VT) of cell 100. Conversely, a logic “0” data bit is written into DRAM cell 100 by biasing drain node 106 to a negative voltage while gate node 111 is biased at a mid-level voltage, thereby forward biasing the floating body-to-drain junction and removing holes from floating body 109, thereby raising the threshold voltage (VT) of cell 100.
A read operation is performed by applying mid-level voltages to both drain node 106 and gate node 111 (while source node 105 remains grounded). Under these conditions, a relatively large drain-to-source current will flow if DRAM cell 100 stores a logic “1” data bit, and a relatively small drain-to source current will flow if DRAM cell 100 stores a logic “0” data bit. The level of the drain-to-source current is compared with the current through a reference cell to determine the difference between a logic “0” and a logic “1” data bit. Non-selected DRAM cells in the same array as DRAM cell 100 have their gate nodes biased to a negative voltage to minimize leakage currents and disturbances from read and write operations.
One significant disadvantage of conventional 1T/FB DRAM cell 100 is that it requires the use of partially depleted silicon-on-insulator (PD-SOI) process, which is relatively expensive and not widely available. In addition, the floating body effect of the SOI process, although utilized in the 1T/FB DRAM cell advantageously, complicates circuit and logic designs significantly and often requires costly substrate connections to eliminate undesired floating body nodes not located in the 1T/FB DRAM cells. Further, with a PD-SOI process, the device leakage characteristics can be difficult to control due to the lack of effective back-gate control of the bottom interface of the silicon layer that includes silicon regions 107–109.
Conventional 1T/FB DRAM cells are described in more detail in “A Capacitor-less 1T-DRAM Cell,” S. Okhonin et al, pp. 85–87, IEEE Electron Device Letters, Vol. 23, No. 2, February 2002, and “Memory Design Using One-Transistor Gain Cell on SOI,” T. Ohsawa et al, pp. 152–153, Tech. Digest, 2002 IEEE International Solid-State Circuits Conference, February 2002.
Therefore, one object of the present invention is to provide a 1T/FB DRAM cell that is compatible with a conventional bulk CMOS process, and is compatible with conventional logic processes and conventional logic designs.
It is another object of the present invention to provide a vertical transistor having a gate electrode located at least partially inside a recessed region formed in a shallow-trench isolation (STI) region, wherein the charge storage body region of the vertical transistor is fully isolated.